In order to ensure proper operation and high-quality of ICs, manufacturing tests must be run on each fabricated device so as to detect structural faults and eliminate defective parts or devices. An IC design typically includes design-for-test (DFT) so as to make the IC design testable or scannable. An automatic test pattern generation (ATPG) tool, such as FastScan™, available from Mentor Graphics® Corporation of Wilsonville, Oreg., produces manufacturing test vectors (scan test patterns) for IC designs. As IC designs grow larger and access to logic becomes more limited, the task of ATPG tools becomes more challenging.
An ATPG tool relies on dedicated ATPG libraries, which is also referred to as design-for-test (DFT) libraries, to generate the test patterns. Such dedicated libraries include ATPG models for modules of the IC design, and are typically generated manually from a source design library which is written in the register-transfer-level language (RTL). However, such manual generation is extremely time-consuming and error prone task, as it includes, for example, RTL modification, removal of certain constructs, gathering information, and writing models. Furthermore, the generated ATPG models are not verified until silicon process is completed. However, ATPG models might be incomplete, for example, missing “stuck_at” detection or having insufficient fault coverage. A substantially long time period (for example, several days) is required for a DFT team to run ATPG on a new circuit design after obtaining a RTL code for the design, including modification of the RTL code, removing some constructs not supported by the ATPG, and writing ATPG models.